;ELMOT.PIC for 18F242 on Board elmot ;Co. Elmar Benninghaus ;78628 Rottweil ;------------------------------------ ;27.06.2005 - V 1.0 ;------------------------------------ include "p18f242.inc" ;------------------------------------ ;configurations ;------------------------------------ ;20Mhz, power-on timer, no watchdog, hs-oscillator __CONFIG _CONFIG1H, _HS_OSC_1H __CONFIG _CONFIG2L, _PWRT_ON_2L __CONFIG _CONFIG2H, _WDT_OFF_2H ;------------------------------------ ;global Definitions ;------------------------------------ #define CPUFREQ D'20000000' ;CPU-Frequency #define SETBANK0 movlb 0x00 #define SETBANK1 movlb 0x01 #define SETBANK2 movlb 0x02 ;------------------------------------ ;AC = ACCESS, BK = BANKED AC EQU 0 BK EQU 1 include "mem.asm" ;programstart org 0x00 goto GENINIT ;high prio interrupt org 0x08 goto INT_SPI ;low prio interrupt org 0x18 goto INT_TIMER ;############# THE INITIALIZATION ####################### GENINIT ;PortA0 MP1SENSE Input Analog (default digital input) ;PortA1 MP2SENSE Input Analog (default digital input) ;PortA2 MP1DIR Output ( low at startup ) ;PortA3 MP2DIR Output ( low at startup ) ;PortA4 ADDR1 Input ;PortA5 SPICS(SS) Input SPI - Slave CS input ;PortB0 MENCA Input Encoder input A ;PortB1 MENCB Input Encoder input B ;PortB2 MP1EN Output L298 Enable (H-active, at startup L) ;PortB3 MP2EN Output L298 Enable (H-active, at startup L) ;PortB4 ADDR0 Input ;PortB5 PGM INPUT h = PROGRAM ICSP l = normal program ;PortB6 PGMCLK INPUT CLOCK ICSP ;PortB7 PGMDATA INPUT DATAIN ICSP ;PortC0 ADDR2 Input ;PortC1 MP2PWM Output ( default low at startup ) ;PortC2 MP1PWM Output ( default low at startup ) ;PortC3 SPICLK Input SPI - Slave clock input ;PortC4 SPIDATAIN Input SPI - Slave datain ;PortC5 SPIDATAOUT Output SPI - Slave dataout ;PortC6 TXT Output Test with LED ( default high at startup ) ;PortC7 RXD Input ;SPI - Mode Slave SS used ;High active clock-level ( idle = low, because this is also when not connect) ;set data when clock rises ( leading edge ) ;sample data when clock fall( falling edge ) ;init porta CLRF PORTA,AC CLRF LATA,AC MOVLW 0x07 MOVWF ADCON1,AC ;default all as digital MOVLW 0xF3 MOVWF TRISA,AC ;11110011 CLRF PORTA,AC ;init portb CLRF PORTB,AC CLRF LATB,AC MOVLW 0xF3 MOVWF TRISB,AC ;11110011 CLRF PORTB,AC ;init portc CLRF PORTC,AC CLRF LATC,AC MOVLW 0x99 MOVWF TRISC,AC ;10011001 MOVLW 0x60 MOVWF PORTC,AC ;01100000 ;setting all to default,saver values CLRF drv_flags,AC CLRF run_flags,AC CLRF work_flags,AC CLRF spec_flags,AC CLRF stepctr,AC CLRF spi_cmd,AC CLRF spi_ctr,AC SETF steplp,AC SETF steplpctr,AC MOVLW D'0032' MOVWF msmax,AC ;set msmax to Fullstep MOVLW D'0001' MOVWF msmin,AC ;set msmin to 1/32 microstepsize MOVWF mscur,AC ;dito for mscur ;getting ADDR0,1,2 and setting spi_addr from it CLRF spi_addr,AC BTFSC PORTC,0,AC ;skip if ADDR2=0 BSF spi_addr,2,AC BTFSC PORTA,4,AC ;skip if ADDR1=0 BSF spi_addr,1,AC BTFSC PORTB,4,AC ;skip if ADDR0=0 BSF spi_addr,0,AC ;ok, now dvr_addr contains the meaned address ;------------------------------------------------- ;init PWM Frq. with PR2, 20 kHz ( if 20 Mhz clock ) ;(period = 0,00005 )(10 bit max duty (100%) 1000 = 0,00005 ), ; ; or 40 kHz ( if 40 Mhz clock ) ;(period = 0,000025)(10 bit max duty (100%) 1000 = 0,000025) ;(max. poss. frq for l298 is 40Mhz, also for pic18f242) ;------------------------------------------------------------------------ MOVLW 0x00 MOVWF TMR2,AC ;clear Timer2 MOVLW 0xF9 ;PR2=PWM Period;0xFF corresponds to Frq MOVWF PR2,AC ;PWM period = [(PR2)+1]*4* 1/sysclock *Tmr2 prescale ; = [255+1] * 4 * 0,00000005 * 1 = 0,000051 MOVLW 0x04 ;Timer2 is ON,prescale = 1:1 MOVWF T2CON,AC ;Load to Timer2 control register MOVLW 0x0c ;Set CCP1 to PWM mode MOVWF CCP1CON,AC MOVLW 0x0c ;Set CCP2 to PWM mode MOVWF CCP2CON,AC ;set motor to a fullstep-value, default direction is right ;means work_flags.RUN_LEFTDOWN is cleared when startup. MOVLW 0xE8 ;Set CCPR1L 100% duty cycle (CCPR1L:CCP1CON<5.4> = 1000 ) MOVWF CCPR1L,AC ;8MSBs of duty cycle MOVLW 0x30 ;2 LSBs at CCPxCON<5:4> IORWF CCP1CON,1,AC MOVLW 0x00 ;set CCPR2L MOVWF CCPR2L,AC ;8MSBs of duty cycle MOVLW B'00000100' ;MP2DIR=0,MP1DIR=1 set Forward current in Winding1 MOVWF PORTA MOVLW B'00001100' ;MP2EN =1,MP1EN =1 on MOVWF PORTB ;------------------------------------------------- ;We have to read encodersignals here to set ;enc_tmp, and enc_tmpold to a proper value CLRF enc_tmp BTFSC PORTB,0,AC BSF enc_tmp,MENCA,AC BTFSC PORTB,1,AC BSF enc_tmp,MENCB,AC MOVFF enc_tmp,enc_tmpold ;------------------------------------------------- ;init spi BCF SSPCON1,SSPEN,AC MOVLW 0x40 MOVWF SSPSTAT,AC ;01000000 transmit when rise MOVLW 0x24 MOVWF SSPCON1,AC ;00100100 no collision, no overflow, ;clock highactive, spi enabled ;clearing, reading SSBUF MOVF SSPBUF,W,AC ;then setting it to 0xff SETF SSPBUF,AC ;init spi - interrupt stuff BCF PIR1,SSPIF ;clear int-req flag BSF RCON,IPEN ;enabling prio-levels BSF IPR1,SSPIP ;setting high prio for spi-int ;( after start, the IPR-regs are all 1 default ) BSF PIE1,SSPIE,AC ;enabling spi-int ;init timer - interrupt stuff BCF INTCON,TMR0IE,AC ;disable TMR0 Overflow int BCF T0CON,TMR0ON,AC ;stops timer 0 BCF INTCON2,TMR0IP,AC ;timer 0 overflow int low priority ;last stuff, enabling general all init interrupts BSF INTCON,PEIE,AC ;enable low-level int BSF INTCON,GIE,AC ;enable high-level int ;-------- TEST - little show loop 3 times, only for showing ;-------- if board is living after programming. ; MOVLW 0x03 ; MOVWF spi_ctr,AC ;testloop: ; BSF PORTC,TX,AC ;testcounta: ; MOVLW 0xff ; MOVWF spi_cmd,AC ;testcountb: ; NOP ; DECFSZ WREG,1,AC ; BRA testcountb ; MOVLW 0xff ; DECFSZ spi_cmd,1,AC ; BRA testcountb ; MOVWF spi_cmd,AC ; BCF PORTC,TX,AC ;testcountc: ; NOP ; DECFSZ WREG,1,AC ; BRA testcountc ; MOVLW 0xff ; DECFSZ spi_cmd,1,AC ; BRA testcountc ; MOVWF spi_cmd,AC ; DECFSZ spi_ctr,1,AC ; BRA testloop ; CLRF spi_cmd,AC ; CLRF spi_ctr,AC ;-------- TESTEND ;TX high, can be used as flag externally for looking ;if board is ready. BSF PORTC,TX,AC ;############# THE PROGRAMLOOP ####################### ;now, - all should be in a proper conditions ;and we can do our programloop, if we use it ;------------------------------------------- GENLOOP ;------- BTFSS drv_flags,INT_HANDLES_CMD,AC CALL CMD_WORK ;if not handled by interrupt, we do it here BTFSS PORTC,RX,AC;skip if high BRA GENLOOP;if bit 7 of portc low, normally loop ;we have a high signal on RXD, so we will wait till it goes ;high again. waitforrxdhigh NOP BTFSC PORTC,RX,AC;skip if low again BRA waitforrxdhigh CALL STEP_WORK GOTO GENLOOP ;starts timer with timerval, called by CMD_WORK start_timer BCF INTCON,TMR0IE,AC ;disable TMR0 Overflow int MOVLW B'10000001' ;Bit 7 = 0 Timer off ;Bit 6 = 0 Timer is 16bit-timer ;Bit 5 = 0 Internal instruction cycle clock ;Bit 4 = 0 We use timermode (cycle clock) ;Bit 3 = 0 prescaler on ;Bit 2,1,0 = 111 = 1:256 ; 110 = 1:128 ; 101 = 1:64 ; 100 = 1:32 ; 011 = 1:16 ; 010 = 1:8 ; 001 = 1:4 we use this ; 000 = 1:2 MOVF timerhigh,W,AC MOVWF TMR0H,AC MOVF timerlow,W,AC MOVWF TMR0L,AC ;this clears also prescaler BCF INTCON,TMR0IF,AC ;clear TMR0 overflow flag BSF INTCON,TMR0IE,AC ;enable TMR0 Overflow int BSF T0CON,TMR0ON,AC ;starts timer 0 RETURN ;13 cycles INT_TIMER BTFSC INTCON,TMR0IF,AC ;Timer0 overflow Interrupt? BRA timer0int RETFIE 0 timer0int BSF T0CON,TMR0ON,AC ;stops timer 0 ;For reason the high-prio INT_SPI will occure, ;we have to save, and restore our values by our own. MOVWF litmp_w,AC MOVFF STATUS, litmp_status MOVFF BSR, litmp_bsr CALL STEP_WORK MOVF timerhigh,W,AC MOVWF TMR0H,AC MOVF timerlow,W,AC MOVWF TMR0L,AC ;this clears also prescaler BCF INTCON,TMR0IF,AC ;clear TMR0 overflow flag BSF T0CON,TMR0ON,AC ;starts timer 0 ;restore regs MOVFF litmp_bsr, BSR MOVF litmp_w, W, AC MOVFF litmp_status, STATUS RETFIE 0 ;24 + max step_work(440) = 464 ;5.000.000 / 464 = 10.775,86 max Frq. include "pos.asm" include "matrix.asm" include "dir.asm" include "step.asm" include "cmd.asm" include "int.asm" ;#################################################### ;######## PWMTABLE ################################## #define CCPCON00 B'00001100' #define CCPCON01 B'00001100' #define CCPCON02 B'00001100' #define CCPCON03 B'00011100' #define CCPCON04 B'00011100' #define CCPCON05 B'00011100' #define CCPCON06 B'00101100' #define CCPCON07 B'00101100' #define CCPCON08 B'00101100' #define CCPCON09 B'00111100' #define CCPCON10 B'00111100' #define CCPCON11 B'00111100' #define CCPCON12 B'00111100' #define CCPCON13 B'00111100' #define CCPCON14 B'00111100' #define CCPCON15 B'00111100' #define CCPCON16 B'00111100' #define CCPRL_00 B'00000000' #define CCPRL_01 B'01100010' #define CCPRL_02 B'11001000' #define CCPRL_03 B'00100010' #define CCPRL_04 B'01111100' #define CCPRL_05 B'11010110' #define CCPRL_06 B'00110000' #define CCPRL_07 B'01110110' #define CCPRL_08 B'11000110' #define CCPRL_09 B'00000010' #define CCPRL_10 B'00111110' #define CCPRL_11 B'01110000' #define CCPRL_12 B'10100010' #define CCPRL_13 B'10111100' #define CCPRL_14 B'11010100' #define CCPRL_15 B'11100011' #define CCPRL_16 B'11101000' #define PORTAHS1 B'00000100' #define PORTAHS2 B'00000100' #define PORTAHS3 B'00000000' #define PORTAHS4 B'00000000' #define PORTAHS5 B'00001000' #define PORTAHS6 B'00001000' #define PORTAHS7 B'00001100' #define PORTAHS8 B'00001100' ;PORTA B'0000XX00' ;MP2DIR,MP1DIR (0x00,0x04,0x08,0x0c) ;CCP1CON B'00XX1100' 10 bit highvalue duty ( XX ) and pwm on ( 0x0c | 0x00,0x10,0x20,0x30 ) ;CCPR1L low value duty 0 - 255 ;CCP2CON B'00XX1100' 10 bit highvalue duty ( XX ) and pwm on ( 0x0c | 0x00,0x10,0x20,0x30 ) ;CCPR2L low value duty 0 - 255 ;here are 1536 bytes. ;every 6byte seqeunce represent a complete 1/32 ms. ;All values can be read directly by program, and as it is put ;to registers, and portA. ;every 6 byte sequence looks like this. ;DB Value for CCP1CON ( set to bit 5.4 ) and bit 3,2 are high ( for pwm on ); ;DB Value for CCPR1L ;DB Value for CCP2CON ( set to bit 5.4 ) and bit 3,2 are high ( for pwm on ) ;DB Value for CCPR2L ;DB dummy ( unused ) ;DB value for porta ( bits 3,2 for MP2DIR,MP1DIR ) ; ;Have a look, that always 2 byte will be packed to one word. ;So program has to read values like this: ;1.) CCPR1L, 2.)CCP1CON, 3.)CCPR2L, 4.)CCP2CON, 5.)PORTAvalue, 6.)unused ;the complete 1536 bytes represents the values for all 4 Fullsteps, ;containing the values for the 16 Microsteps per halfstep. (sinusoidal) ;the internal stepctr will be multiplicated with 6 to build a valid offset. ;the starting address must be in the normal program-mem, and a even number, ;so furthermore settings of TBLPTR affects only to TBLPTRH,TBLPTHL org 0x3000 pwmtable ; ccp1con, ccpr1l, ccp2con, ccpr2l, dummy, porta ;-------------------------------------------------------------------------- ;FS1-HS1 fs1hs1__cc1_00 DB CCPCON16, CCPRL_16, CCPCON00, CCPRL_00, 0x00, PORTAHS1 fs1hs1__cc1_01 DB CCPCON16, CCPRL_16, CCPCON01, CCPRL_01, 0x00, PORTAHS1 fs1hs1__cc1_02 DB CCPCON16, CCPRL_16, CCPCON02, CCPRL_02, 0x00, PORTAHS1 fs1hs1__cc1_03 DB CCPCON16, CCPRL_16, CCPCON03, CCPRL_03, 0x00, PORTAHS1 fs1hs1__cc1_04 DB CCPCON16, CCPRL_16, CCPCON04, CCPRL_04, 0x00, PORTAHS1 fs1hs1__cc1_05 DB CCPCON16, CCPRL_16, CCPCON05, CCPRL_05, 0x00, PORTAHS1 fs1hs1__cc1_06 DB CCPCON16, CCPRL_16, CCPCON06, CCPRL_06, 0x00, PORTAHS1 fs1hs1__cc1_07 DB CCPCON16, CCPRL_16, CCPCON07, CCPRL_07, 0x00, PORTAHS1 fs1hs1__cc1_08 DB CCPCON16, CCPRL_16, CCPCON08, CCPRL_08, 0x00, PORTAHS1 fs1hs1__cc1_09 DB CCPCON16, CCPRL_16, CCPCON09, CCPRL_09, 0x00, PORTAHS1 fs1hs1__cc1_10 DB CCPCON16, CCPRL_16, CCPCON10, CCPRL_10, 0x00, PORTAHS1 fs1hs1__cc1_11 DB CCPCON16, CCPRL_16, CCPCON11, CCPRL_11, 0x00, PORTAHS1 fs1hs1__cc1_12 DB CCPCON16, CCPRL_16, CCPCON12, CCPRL_12, 0x00, PORTAHS1 fs1hs1__cc1_13 DB CCPCON16, CCPRL_16, CCPCON13, CCPRL_13, 0x00, PORTAHS1 fs1hs1__cc1_14 DB CCPCON16, CCPRL_16, CCPCON14, CCPRL_14, 0x00, PORTAHS1 fs1hs1__cc1_15 DB CCPCON16, CCPRL_16, CCPCON15, CCPRL_15, 0x00, PORTAHS1 ;FS1-HS2 fs1hs2__cc1_00 DB CCPCON16, CCPRL_16, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_01 DB CCPCON15, CCPRL_15, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_02 DB CCPCON14, CCPRL_14, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_03 DB CCPCON13, CCPRL_13, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_04 DB CCPCON12, CCPRL_12, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_05 DB CCPCON11, CCPRL_11, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_06 DB CCPCON10, CCPRL_10, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_07 DB CCPCON09, CCPRL_09, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_08 DB CCPCON08, CCPRL_08, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_09 DB CCPCON07, CCPRL_07, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_10 DB CCPCON06, CCPRL_06, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_11 DB CCPCON05, CCPRL_05, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_12 DB CCPCON04, CCPRL_04, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_13 DB CCPCON03, CCPRL_03, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_14 DB CCPCON02, CCPRL_02, CCPCON16, CCPRL_16, 0x00, PORTAHS2 fs1hs2__cc1_15 DB CCPCON01, CCPRL_01, CCPCON16, CCPRL_16, 0x00, PORTAHS2 ;FS2-HS3 fs2hs1__cc1_00 DB CCPCON00, CCPRL_00, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_01 DB CCPCON01, CCPRL_01, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_02 DB CCPCON02, CCPRL_02, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_03 DB CCPCON03, CCPRL_03, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_04 DB CCPCON04, CCPRL_04, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_05 DB CCPCON05, CCPRL_05, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_06 DB CCPCON06, CCPRL_06, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_07 DB CCPCON07, CCPRL_07, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_08 DB CCPCON08, CCPRL_08, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_09 DB CCPCON09, CCPRL_09, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_10 DB CCPCON10, CCPRL_10, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_11 DB CCPCON11, CCPRL_11, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_12 DB CCPCON12, CCPRL_12, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_13 DB CCPCON13, CCPRL_13, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_14 DB CCPCON14, CCPRL_14, CCPCON16, CCPRL_16, 0x00, PORTAHS3 fs2hs1__cc1_15 DB CCPCON15, CCPRL_15, CCPCON16, CCPRL_16, 0x00, PORTAHS3 ;FS2-HS4 fs2hs2__cc1_00 DB CCPCON16, CCPRL_16, CCPCON16, CCPRL_16, 0x00, PORTAHS4 fs2hs2__cc1_01 DB CCPCON16, CCPRL_16, CCPCON15, CCPRL_15, 0x00, PORTAHS4 fs2hs2__cc1_02 DB CCPCON16, CCPRL_16, CCPCON14, CCPRL_14, 0x00, PORTAHS4 fs2hs2__cc1_03 DB CCPCON16, CCPRL_16, CCPCON13, CCPRL_13, 0x00, PORTAHS4 fs2hs2__cc1_04 DB CCPCON16, CCPRL_16, CCPCON12, CCPRL_12, 0x00, PORTAHS4 fs2hs2__cc1_05 DB CCPCON16, CCPRL_16, CCPCON11, CCPRL_11, 0x00, PORTAHS4 fs2hs2__cc1_06 DB CCPCON16, CCPRL_16, CCPCON10, CCPRL_10, 0x00, PORTAHS4 fs2hs2__cc1_07 DB CCPCON16, CCPRL_16, CCPCON09, CCPRL_09, 0x00, PORTAHS4 fs2hs2__cc1_08 DB CCPCON16, CCPRL_16, CCPCON08, CCPRL_08, 0x00, PORTAHS4 fs2hs2__cc1_09 DB CCPCON16, CCPRL_16, CCPCON07, CCPRL_07, 0x00, PORTAHS4 fs2hs2__cc1_10 DB CCPCON16, CCPRL_16, CCPCON06, CCPRL_06, 0x00, PORTAHS4 fs2hs2__cc1_11 DB CCPCON16, CCPRL_16, CCPCON05, CCPRL_05, 0x00, PORTAHS4 fs2hs2__cc1_12 DB CCPCON16, CCPRL_16, CCPCON04, CCPRL_04, 0x00, PORTAHS4 fs2hs2__cc1_13 DB CCPCON16, CCPRL_16, CCPCON03, CCPRL_03, 0x00, PORTAHS4 fs2hs2__cc1_14 DB CCPCON16, CCPRL_16, CCPCON02, CCPRL_02, 0x00, PORTAHS4 fs2hs2__cc1_15 DB CCPCON16, CCPRL_16, CCPCON01, CCPRL_01, 0x00, PORTAHS4 ;FS3-HS5 fs3hs1__cc1_00 DB CCPCON16, CCPRL_16, CCPCON00, CCPRL_00, 0x00, PORTAHS5 fs3hs1__cc1_01 DB CCPCON16, CCPRL_16, CCPCON01, CCPRL_01, 0x00, PORTAHS5 fs3hs1__cc1_02 DB CCPCON16, CCPRL_16, CCPCON02, CCPRL_02, 0x00, PORTAHS5 fs3hs1__cc1_03 DB CCPCON16, CCPRL_16, CCPCON03, CCPRL_03, 0x00, PORTAHS5 fs3hs1__cc1_04 DB CCPCON16, CCPRL_16, CCPCON04, CCPRL_04, 0x00, PORTAHS5 fs3hs1__cc1_05 DB CCPCON16, CCPRL_16, CCPCON05, CCPRL_05, 0x00, PORTAHS5 fs3hs1__cc1_06 DB CCPCON16, CCPRL_16, CCPCON06, CCPRL_06, 0x00, PORTAHS5 fs3hs1__cc1_07 DB CCPCON16, CCPRL_16, CCPCON07, CCPRL_07, 0x00, PORTAHS5 fs3hs1__cc1_08 DB CCPCON16, CCPRL_16, CCPCON08, CCPRL_08, 0x00, PORTAHS5 fs3hs1__cc1_09 DB CCPCON16, CCPRL_16, CCPCON09, CCPRL_09, 0x00, PORTAHS5 fs3hs1__cc1_10 DB CCPCON16, CCPRL_16, CCPCON10, CCPRL_10, 0x00, PORTAHS5 fs3hs1__cc1_11 DB CCPCON16, CCPRL_16, CCPCON11, CCPRL_11, 0x00, PORTAHS5 fs3hs1__cc1_12 DB CCPCON16, CCPRL_16, CCPCON12, CCPRL_12, 0x00, PORTAHS5 fs3hs1__cc1_13 DB CCPCON16, CCPRL_16, CCPCON13, CCPRL_13, 0x00, PORTAHS5 fs3hs1__cc1_14 DB CCPCON16, CCPRL_16, CCPCON14, CCPRL_14, 0x00, PORTAHS5 fs3hs1__cc1_15 DB CCPCON16, CCPRL_16, CCPCON15, CCPRL_15, 0x00, PORTAHS5 ;FS3-HS6 fs3hs2__cc1_00 DB CCPCON16, CCPRL_16, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_01 DB CCPCON15, CCPRL_15, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_02 DB CCPCON14, CCPRL_14, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_03 DB CCPCON13, CCPRL_13, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_04 DB CCPCON12, CCPRL_12, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_05 DB CCPCON11, CCPRL_11, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_06 DB CCPCON10, CCPRL_10, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_07 DB CCPCON09, CCPRL_09, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_08 DB CCPCON08, CCPRL_08, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_09 DB CCPCON07, CCPRL_07, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_10 DB CCPCON06, CCPRL_06, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_11 DB CCPCON05, CCPRL_05, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_12 DB CCPCON04, CCPRL_04, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_13 DB CCPCON03, CCPRL_03, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_14 DB CCPCON02, CCPRL_02, CCPCON16, CCPRL_16, 0x00, PORTAHS6 fs3hs2__cc1_15 DB CCPCON01, CCPRL_01, CCPCON16, CCPRL_16, 0x00, PORTAHS6 ;FS4-HS7 fs4hs1__cc1_00 DB CCPCON00, CCPRL_00, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_01 DB CCPCON01, CCPRL_01, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_02 DB CCPCON02, CCPRL_02, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_03 DB CCPCON03, CCPRL_03, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_04 DB CCPCON04, CCPRL_04, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_05 DB CCPCON05, CCPRL_05, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_06 DB CCPCON06, CCPRL_06, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_07 DB CCPCON07, CCPRL_07, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_08 DB CCPCON08, CCPRL_08, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_09 DB CCPCON09, CCPRL_09, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_10 DB CCPCON10, CCPRL_10, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_11 DB CCPCON11, CCPRL_11, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_12 DB CCPCON12, CCPRL_12, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_13 DB CCPCON13, CCPRL_13, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_14 DB CCPCON14, CCPRL_14, CCPCON16, CCPRL_16, 0x00, PORTAHS7 fs4hs1__cc1_15 DB CCPCON15, CCPRL_15, CCPCON16, CCPRL_16, 0x00, PORTAHS7 ;FS4-HS8 fs4hs2__cc1_00 DB CCPCON16, CCPRL_16, CCPCON16, CCPRL_16, 0x00, PORTAHS8 fs4hs2__cc1_01 DB CCPCON16, CCPRL_16, CCPCON15, CCPRL_15, 0x00, PORTAHS8 fs4hs2__cc1_02 DB CCPCON16, CCPRL_16, CCPCON14, CCPRL_14, 0x00, PORTAHS8 fs4hs2__cc1_03 DB CCPCON16, CCPRL_16, CCPCON13, CCPRL_13, 0x00, PORTAHS8 fs4hs2__cc1_04 DB CCPCON16, CCPRL_16, CCPCON12, CCPRL_12, 0x00, PORTAHS8 fs4hs2__cc1_05 DB CCPCON16, CCPRL_16, CCPCON11, CCPRL_11, 0x00, PORTAHS8 fs4hs2__cc1_06 DB CCPCON16, CCPRL_16, CCPCON10, CCPRL_10, 0x00, PORTAHS8 fs4hs2__cc1_07 DB CCPCON16, CCPRL_16, CCPCON09, CCPRL_09, 0x00, PORTAHS8 fs4hs2__cc1_08 DB CCPCON16, CCPRL_16, CCPCON08, CCPRL_08, 0x00, PORTAHS8 fs4hs2__cc1_09 DB CCPCON16, CCPRL_16, CCPCON07, CCPRL_07, 0x00, PORTAHS8 fs4hs2__cc1_10 DB CCPCON16, CCPRL_16, CCPCON06, CCPRL_06, 0x00, PORTAHS8 fs4hs2__cc1_11 DB CCPCON16, CCPRL_16, CCPCON05, CCPRL_05, 0x00, PORTAHS8 fs4hs2__cc1_12 DB CCPCON16, CCPRL_16, CCPCON04, CCPRL_04, 0x00, PORTAHS8 fs4hs2__cc1_13 DB CCPCON16, CCPRL_16, CCPCON03, CCPRL_03, 0x00, PORTAHS8 fs4hs2__cc1_14 DB CCPCON16, CCPRL_16, CCPCON02, CCPRL_02, 0x00, PORTAHS8 fs4hs2__cc1_15 DB CCPCON16, CCPRL_16, CCPCON01, CCPRL_01, 0x00, PORTAHS8 ;######################################################################## ;######################### EEPROM DATAS ################################# ;######################################################################## ;ee_diddel DE 0x00,0x01,0x02,0x03 end